This invention relates in general to visual displays for electronic devices and more particularly to an improved emitter substructure for active matrix field emission displays.
FIG. 1 is a simplified side cross-sectional view of a portion of a display 10 including a faceplate 20 and a baseplate 21 in accordance with the prior art. FIG. 1 is not drawn to scale. The faceplate 20 includes a transparent viewing screen 22, a transparent conductive layer 24 and a cathodoluminescent layer 26. The transparent viewing screen 22 supports the layers 24 and 26, acts as a viewing surface and as a wall for a hermetically sealed package formed between the viewing screen 22 and the baseplate 21. The viewing screen 22 may be formed from glass. The transparent conductive layer 24 may be formed from indium tin oxide. The cathodoluminescent layer 26 may be segmented into pixels yielding different colors for color displays. Materials useful as cathodoluminescent materials in the cathodoluminescent layer 26 include Y2O3:Eu (red, phosphor P-56), Y3(Al, Ga)5O12:Tb (green, phosphor P-53) and Y2(SiOs):Ce (blue, phosphor P-47) available from Osram Sylvania of Towanda PA or from Nichia of Japan.
The baseplate 21 includes emitters 30 formed on a planar surface of a semiconductor substrate 32. The substrate 32 is coated with a dielectric layer 34. In one embodiment, this is effected by deposition of silicon dioxide via a conventional TEOS process. The dielectric layer 34 is formed to have a thickness, measured in a direction perpendicular to a surface of the substrate 32 as indicated by direction arrow 36, that is approximately equal to or just less than a height of the emitters 30. This thickness is on the order of 0.4 microns, although greater or lesser thicknesses may be employed. An extraction grid 38 comprising a conductive material is formed on the dielectric layer 34. The extraction grid 38 may be realized, for example, as a thin layer of polysilicon. The radius of an opening 40 created in the extraction grid 38, which is also approximately the separation of the extraction grid 38 from the tip of the emitter 30, is about 0.4 microns, although larger or smaller openings 40 may also be employed. This separation is defined herein to mean beingxe2x80x9cin close proximity.xe2x80x9d
Another dielectric layer 42 is formed on the extraction grid 38. A chemical isolation layer 44, such as titanium, is formed on the dielectric layer 42. A soft X-ray blocking layer 46, such as tungsten, is formed on the chemical isolation layer 44 for reasons that will be explained below.
The baseplate 21 also includes a field effect transistor (xe2x80x9cFETxe2x80x9d) 50 formed in the surface of the substrate 32 for controlling the supply of electrons to the emitter 30. The FET 50 includes an n-tank 52 formed in the surface of the substrate 32 beneath the emitter 30. The n-tank 52 serves as a drain for the FET 50, and may be formed via conventional masking and ion implantation processes. The FET 50 also includes a source 54 and a gate electrode 56. The gate electrode 56 is separated from the substrate 32 by a gate oxide layer 57 and a field oxide layer 58.
The substrate 32 may be formed from p-type silicon material having an acceptor concentration NA ca. 1-5+1015/cm3, while the n-tank 52 may have a surface donor concentration ND ca. 1-2+1016/cm3. A depletion region 60 is formed at a p-n junction between the n-tank 52 and the p-type substrate 32. The depletion region 60 provides electrical isolation from other circuitry contained on or integrated in the substrate 32. These values for the acceptor and donor concentrations allow the FET 50 to operate at the voltages required for displays 10 and provides a higher avalanche breakdown voltage than would be provided by, e.g., transistors used in conventional CMOS logic circuitry. The capacitance of the depletion region 60 is reduced compared to that of conventional logic circuitry because the doping levels are less and the operating voltages are higher, resulting in a larger depletion region 60 than would exist for transistors used in conventional logic circuitry. This provides increased electrical isolation of the FET 50 from other circuitry integrated into the substrate 32, compared to transistors used in conventional logic circuitry.
In operation, the extraction grid 38 is biased to a voltage on the order of 40-80 volts, although higher or lower voltages may be used, while the substrate 32 is maintained at a voltage of about zero volts. Signals coupled to the gate 56 of the FET 50 turn the FET 50 on, allowing electrons to flow from the source 54 to the n-tank 52 and thus to the emitter 30. Intense electrical fields between the emitter 30 and the extraction grid 38 then cause field emission of electrons from the emitter 30. A larger positive voltage, ranging up to as much as 5,000 volts or more but often 2,500 volts or less, is applied to the faceplate 20 via the transparent conductive layer 24. The electrons emitted from the emitter 30 are accelerated to the faceplate 20 by this voltage and strike the cathodoluminescent layer 26. This causes light emission in selected areas, i.e., those areas adjacent to where the FETs 50 are conducting, and fonns luminous images such as text, pictures and the like. Integrating the FETs 50 in the substrate 32 to provide an active display 10 yields advantages in size, simplicity and ease of interconnection of the display 10 to other electronic componentry.
Visible photons from the cathodoluminescent layer 26 and photons that travel through the faceplate 20 can also travel back through the openings 40. When photons travel through portions of the extraction grid 38 that are exposed by the openings 40 and impinge on the depletion region 60, electron-hole pairs are generated. When electron-hole pairs are produced within the depletion region 60 associated with the p-n junction between the. n-tank 52 and the p-type substrate 21, the electrons and holes are efficiently separated by the electrical fields associated with the depletion region 60. The electrons are swept into the n-tank 52 and the holes are swept into the p-type substrate 32 surrounding the n-tank 52. The electrons provide an undesirable component to electrons emitted by the emitter 30. This results in distortion in the images produced by the display 10.
For example, a blue pixel emitting blue light could provide a photon that reaches semiconductor material underlying the emitter 30 associated with an adjacent red pixel, which is not intended to be emitting light. This may cause an emitter current component resulting in an anode current in the red pixel, thus providing unwanted red light and thereby distorting the color intended to be displayed.
Alternatively, an area intended to be a dark area in the display 10 may emit light when that area is exposed to high ambient light conditions. These effects are undesirable and tend to reduce display dynamic range in addition to distorting the intended image.
There is therefore a need for a way to render p-n junctions associated with monolithic emitters less sensitive to incident photons for use in field emission displays.
Various aspects of the present invention include an emitter substrate and methods for manufacturing the substrate as well as displays incorporating the substrate and a computer using the substrate. The inventive substrate includes a semiconductor material of one type in which a tank of the opposite type semiconductor material is formed. An emitter is formed on and electrically coupled to the tank. An insulating region is formed at a lower boundary of the tank. The insulating region electrically isolates the emitter and the tank along at least a portion of the lower boundary. As a result, a depletion region associated with a boundary between the substrate material and the tank is displaced from that area where photons may impinge. This reduces distortion in the display.